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- {"ast":null,"code":"/*\nLanguage: VHDL\nAuthor: Igor Kalnitsky <igor@kalnitsky.org>\nContributors: Daniel C.K. Kho <daniel.kho@tauhop.com>, Guillaume Savaton <guillaume.savaton@eseo.fr>\nDescription: VHDL is a hardware description language used in electronic design automation to describe digital and mixed-signal systems.\nWebsite: https://en.wikipedia.org/wiki/VHDL\nCategory: hardware\n*/\n\nfunction vhdl(hljs) {\n // Regular expression for VHDL numeric literals.\n\n // Decimal literal:\n const INTEGER_RE = '\\\\d(_|\\\\d)*';\n const EXPONENT_RE = '[eE][-+]?' + INTEGER_RE;\n const DECIMAL_LITERAL_RE = INTEGER_RE + '(\\\\.' + INTEGER_RE + ')?' + '(' + EXPONENT_RE + ')?';\n // Based literal:\n const BASED_INTEGER_RE = '\\\\w+';\n const BASED_LITERAL_RE = INTEGER_RE + '#' + BASED_INTEGER_RE + '(\\\\.' + BASED_INTEGER_RE + ')?' + '#' + '(' + EXPONENT_RE + ')?';\n const NUMBER_RE = '\\\\b(' + BASED_LITERAL_RE + '|' + DECIMAL_LITERAL_RE + ')';\n const KEYWORDS = [\"abs\", \"access\", \"after\", \"alias\", \"all\", \"and\", \"architecture\", \"array\", \"assert\", \"assume\", \"assume_guarantee\", \"attribute\", \"begin\", \"block\", \"body\", \"buffer\", \"bus\", \"case\", \"component\", \"configuration\", \"constant\", \"context\", \"cover\", \"disconnect\", \"downto\", \"default\", \"else\", \"elsif\", \"end\", \"entity\", \"exit\", \"fairness\", \"file\", \"for\", \"force\", \"function\", \"generate\", \"generic\", \"group\", \"guarded\", \"if\", \"impure\", \"in\", \"inertial\", \"inout\", \"is\", \"label\", \"library\", \"linkage\", \"literal\", \"loop\", \"map\", \"mod\", \"nand\", \"new\", \"next\", \"nor\", \"not\", \"null\", \"of\", \"on\", \"open\", \"or\", \"others\", \"out\", \"package\", \"parameter\", \"port\", \"postponed\", \"procedure\", \"process\", \"property\", \"protected\", \"pure\", \"range\", \"record\", \"register\", \"reject\", \"release\", \"rem\", \"report\", \"restrict\", \"restrict_guarantee\", \"return\", \"rol\", \"ror\", \"select\", \"sequence\", \"severity\", \"shared\", \"signal\", \"sla\", \"sll\", \"sra\", \"srl\", \"strong\", \"subtype\", \"then\", \"to\", \"transport\", \"type\", \"unaffected\", \"units\", \"until\", \"use\", \"variable\", \"view\", \"vmode\", \"vprop\", \"vunit\", \"wait\", \"when\", \"while\", \"with\", \"xnor\", \"xor\"];\n const BUILT_INS = [\"boolean\", \"bit\", \"character\", \"integer\", \"time\", \"delay_length\", \"natural\", \"positive\", \"string\", \"bit_vector\", \"file_open_kind\", \"file_open_status\", \"std_logic\", \"std_logic_vector\", \"unsigned\", \"signed\", \"boolean_vector\", \"integer_vector\", \"std_ulogic\", \"std_ulogic_vector\", \"unresolved_unsigned\", \"u_unsigned\", \"unresolved_signed\", \"u_signed\", \"real_vector\", \"time_vector\"];\n const LITERALS = [\n // severity_level\n \"false\", \"true\", \"note\", \"warning\", \"error\", \"failure\",\n // textio\n \"line\", \"text\", \"side\", \"width\"];\n return {\n name: 'VHDL',\n case_insensitive: true,\n keywords: {\n keyword: KEYWORDS,\n built_in: BUILT_INS,\n literal: LITERALS\n },\n illegal: /\\{/,\n contains: [hljs.C_BLOCK_COMMENT_MODE,\n // VHDL-2008 block commenting.\n hljs.COMMENT('--', '$'), hljs.QUOTE_STRING_MODE, {\n className: 'number',\n begin: NUMBER_RE,\n relevance: 0\n }, {\n className: 'string',\n begin: '\\'(U|X|0|1|Z|W|L|H|-)\\'',\n contains: [hljs.BACKSLASH_ESCAPE]\n }, {\n className: 'symbol',\n begin: '\\'[A-Za-z](_?[A-Za-z0-9])*',\n contains: [hljs.BACKSLASH_ESCAPE]\n }]\n };\n}\nmodule.exports = vhdl;","map":{"version":3,"names":["vhdl","hljs","INTEGER_RE","EXPONENT_RE","DECIMAL_LITERAL_RE","BASED_INTEGER_RE","BASED_LITERAL_RE","NUMBER_RE","KEYWORDS","BUILT_INS","LITERALS","name","case_insensitive","keywords","keyword","built_in","literal","illegal","contains","C_BLOCK_COMMENT_MODE","COMMENT","QUOTE_STRING_MODE","className","begin","relevance","BACKSLASH_ESCAPE","module","exports"],"sources":["F:/workspace/202226701027/huinongbao-app/node_modules/highlight.js/lib/languages/vhdl.js"],"sourcesContent":["/*\nLanguage: VHDL\nAuthor: Igor Kalnitsky <igor@kalnitsky.org>\nContributors: Daniel C.K. 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\"restrict_guarantee\",\n \"return\",\n \"rol\",\n \"ror\",\n \"select\",\n \"sequence\",\n \"severity\",\n \"shared\",\n \"signal\",\n \"sla\",\n \"sll\",\n \"sra\",\n \"srl\",\n \"strong\",\n \"subtype\",\n \"then\",\n \"to\",\n \"transport\",\n \"type\",\n \"unaffected\",\n \"units\",\n \"until\",\n \"use\",\n \"variable\",\n \"view\",\n \"vmode\",\n \"vprop\",\n \"vunit\",\n \"wait\",\n \"when\",\n \"while\",\n \"with\",\n \"xnor\",\n \"xor\"\n ];\n const BUILT_INS = [\n \"boolean\",\n \"bit\",\n \"character\",\n \"integer\",\n \"time\",\n \"delay_length\",\n \"natural\",\n \"positive\",\n \"string\",\n \"bit_vector\",\n \"file_open_kind\",\n \"file_open_status\",\n \"std_logic\",\n \"std_logic_vector\",\n \"unsigned\",\n \"signed\",\n \"boolean_vector\",\n \"integer_vector\",\n \"std_ulogic\",\n \"std_ulogic_vector\",\n \"unresolved_unsigned\",\n \"u_unsigned\",\n \"unresolved_signed\",\n \"u_signed\",\n \"real_vector\",\n \"time_vector\"\n ];\n const LITERALS = [\n // severity_level\n \"false\",\n \"true\",\n \"note\",\n \"warning\",\n \"error\",\n \"failure\",\n // textio\n \"line\",\n \"text\",\n \"side\",\n \"width\"\n ];\n\n return {\n name: 'VHDL',\n case_insensitive: true,\n keywords: {\n keyword: KEYWORDS,\n built_in: BUILT_INS,\n literal: LITERALS\n },\n illegal: /\\{/,\n contains: [\n hljs.C_BLOCK_COMMENT_MODE, // VHDL-2008 block commenting.\n hljs.COMMENT('--', '$'),\n hljs.QUOTE_STRING_MODE,\n {\n className: 'number',\n begin: NUMBER_RE,\n relevance: 0\n },\n {\n className: 'string',\n begin: '\\'(U|X|0|1|Z|W|L|H|-)\\'',\n contains: [ hljs.BACKSLASH_ESCAPE ]\n },\n {\n className: 'symbol',\n begin: '\\'[A-Za-z](_?[A-Za-z0-9])*',\n contains: [ hljs.BACKSLASH_ESCAPE ]\n }\n ]\n };\n}\n\nmodule.exports = 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